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34 www.xilinx.com Development System Reference Guide
Chapter 2: Design Flow
R
In hierarchical designing, a specific hierarchical name identifies each library element,
unique block, and instance you create. The following example shows a hierarchical name
with a 2-input OR gate in the first instance of a multiplexer in a 4-bit counter:
/Acc/alu_1/mult_4/8count_3/4bit_0/mux_1/or2
Xilinx strongly recommends that you name the components and nets in your design. These
names are preserved and used by the FPGA Editor tool. These names are also used for
back-annotation and appear in the debug and analysis tools. If you do not name your
components and nets, the schematic editor automatically generates the names. For
example, if left unnamed, the software might name the previous example, as follows:
/$1a123/$1b942/$1c23/$1d235/$1e121/$1g123/$1h57
Note: It is difficult to analyze circuits with automatically generated names, because the names only
have meaning for Xilinx software.
Schematic Entry Overview
Schematic tools provide a graphic interface for design entry. You can use these tools to
connect symbols representing the logic components in your design. You can build your
design with individual gates, or you can combine gates to create functional blocks. This
section focuses on ways to enter functional blocks using library elements and the CORE
Generator.
Library Elements
Primitives and macros are the “building blocks” of component libraries. Xilinx libraries
provide primitives, as well as common high-level macro functions. Primitives are basic
circuit elements, such as AND and OR gates. Each primitive has a unique library name,
symbol, and description. Macros contain multiple library elements, which can include
primitives and other macros.
You can use the following types of macros with Xilinx FPGAs:
• Soft macros have pre-defined functionality but have flexible mapping, placement, and
routing. Soft macros are available for all FPGAs.
• Relationally placed macros (RPMs) have fixed mapping and relative placement.
RPMs are available for all device families, except the XC9500 family.
Macros are not available for synthesis because synthesis tools have their own module
generators and do not require RPMs. If you wish to override the module generation, you
can instantiate CORE Generator modules. For most leading-edge synthesis tools, this does
not offer an advantage unless it is for a module that cannot be inferred.
CORE Generator Tool (FPGAs Only)
The Xilinx CORE Generator design tool delivers parameterizable cores that are optimized
for Xilinx FPGAs. The library includes cores ranging from simple delay elements to
complex DSP (Digital Signal Processing) filters and multiplexers. For details, refer to the
CORE Generator Guide. You can also refer to the Xilinx IP (Intellectual Property) Center
Web site at http://www.xilinx.com/ipcenter
, which offers the latest IP solutions. These
solutions include design reuse tools, free reference designs, DSP and PCI solutions, IP
implementation tools, cores, specialized system level services, and vertical application IP
solutions.