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418 www.xilinx.com Development System Reference Guide
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state
A state is the set of values stored in the memory elements of a device
(flip-flops, RAMs, CLB outputs, and IOBs) that represent the state of
that device at a particular point of the readback cycle. To each state
there corresponds a specific set of logical values.
state machine
A state machine is a set of combinatorial and sequential logic elements
arranged to operate in a predefined sequence in response to specified
inputs. The hardware implementation of a state machine design is a
set of storage registers (flip-flops) and combinatorial logic, or gates.
The storage registers store the current state, and the logic network
performs the operations to determine the next state.
static timing analysis
A static timing analysis is a point-to-point delay analysis of a design
network.
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TAEngine
A program that performs static timing analysis on a successfully
implemented Xilinx CPLD design (VM6).
TCL
Tool Command Language (Tcl) is an easy to use scripting language
and an industry standard popular in the electronic design automation
(EDA) industry.
TEKHEX (Tektronix)
TEKHEX (Tektronix) is a PROM format supported by Xilinx. Its
maximum address is 65 536. This format supports PROM files of up to
(8 x 65 536) = 524 288 bits.
testbench
An HDL netlist containing test vectors to drive a simulation.
threshold
The threshold is the crossover point when something occurs or is
observed or indicated. The CMOS threshold and TTL threshold are
examples.
timing
Timing is the process that calculates the delays associated with each of
the routed nets in the design.