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Development System Reference Guide www.xilinx.com 43
Design Verification
R
The following figures show the back-annotation flows:
Figure 2-9: Back-Annotation Flow for FPGAs
Figure 2-10: Back-Annotation (CPLDs)
X10298
PAR
NetGen
MAP
NGD
Logical Design
NCD
Physical Design
(Mapped)
NCD
Physical Design
(Placed and Routed)
Simulation Netlist
Equivalence Checking
Netlist
Static Timing Analysis
Netlist
PCF
NCD
X10297
TSIM
Timing Simulator
NetGen
Optimization
and Fitting
NGD
Logical Design
VM6
Physical Design
NGA
EDIF
VHD
SDF
SDF
V
Command line only