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Development System Reference Guide www.xilinx.com 37
Design Implementation
R
The following figure shows the design implementation process for FPGA designs:
Figure 2-5: Design Implementation Flow (FPGAs)
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Constraints Editor
NGD
UCF
BIT
MAP
Floorplanner
TRACE &
Timing Analyzer
PAR
iMPACT
PROMGen
BitGen
NCD
NGDBuild
FPGA Editor
NCD & PCF