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272 www.xilinx.com Development System Reference Guide
Chapter 14: BitGen
R
SEURepair
This option supports single event upset repair by writing bitstreams a single frame at a
time, rather than in one packet. Frame Address Register (FAR) headers are written to
sequentially. First the FRAME address is written to, followed by the FRAME data.
StartCBC
Sets the starting cipher block chaining (CBC) value. The pick option causes BitGen to select
a random number for the value.
StartKey
Sets the starting key number.
StartupClk
The startup sequence following the configuration of a device can be synchronized to either
Cclk, a User Clock, or the JTAG Clock. The default is Cclk.
• Cclk
Enter Cclk to synchronize to an internal clock provided in the FPGA device.
• JTAG Clock
Enter JtagClk to synchronize to the clock provided by JTAG. This clock sequences the
TAP controller which provides the control logic for JTAG.
• UserClk
Enter UserClk to synchronize to a user-defined signal connected to the CLK pin of the
STARTUP symbol.
Architectures: Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3E
Settings: No, Yes
Default: No
Architectures: Virtex-II, Virtex-II Pro, Virtex-4,
Settings: Pick, hex_string
Default: Pick
Architectures: Virtex-II, Virtex-II Pro
Settings: 0, 3
Default: 0
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan 3, and Spartan- 3E
Settings: Cclk (pin—see Note), UserClk (user-supplied), JtagCLK
Default: Cclk