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338 www.xilinx.com Development System Reference Guide
Chapter 22: NetGen
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The [module_name] is the name of the hierarchical module from the front-end that the user
is already familiar with. There are cases when the [module_name] could differ, they are:
• If multiple instances of a module are used in the design, then each instantiation of the
module is unique because the timing for the module is different. The names are made
unique by appending an underscore followed by a “INST_” string and a count value
(e.g., numgen, numgen_INST_1, numgen_INST_2).
• If a new filename clashes with an existing filename within the name scope, then the
new name will be [module_name]_[instance_name].
Testbench File
A testbench file is created for the top-level design when the -tb option is used. The base
name of the testbench file is the same as the base name of the design, with a .tv extension
for Verilog, and a .tvhd extension for VHDL.
Hierarchy Information File
In addition to writing separate netlists, NetGen also generates a separate text file
comprised of hierarchy information. The following information appears in the hierarchy
text file. NONE appears if one of the files does not have relative information.
// Module : The name of the hierarchical design module.
// Instance : The instance name used in the parent module.
// Design File : The name of the file that contains the module.
// SDF File : The SDF file associated with the module.
// SubModule : The sub module(s) contained within a given module.
// Module, Instance : The sub module and instance names.
Note: The hierarchy information file for a top-level design does not contain an Instance field.
The base name of the hierarchy information file is:
[design_base_name]_mhf_info.txt
The STARTUP block is only supported on the top-level design module. The global set reset
(GSR) and global tristate signal (GTS) connectivity of the design is maintained as described
in the “Dedicated Global Signals in Back-Annotation Simulation” section of this chapter.
Dedicated Global Signals in Back-Annotation Simulation
The global set reset (GSR), PRLD for CPLDs, signal and global tristate signal (GTS) are
global routing nets present in the design that provide a means of setting, resetting, or
tristating applicable components in the device. The simulation behavior of these signals is
modeled in the library cells of the Xilinx Simprim library and the simulation netlist using
the glbl module in Verilog and the X_ROC / X_TOC components in VHDL.
The following sections explain the connectivity for Verilog and VHDL netlists.