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Development System Reference Guide www.xilinx.com 31
Design Flow Overview
R
The following figure shows the Xilinx software flow chart for FPGA designs.
Figure 2-2: Xilinx Software Design Flow (FPGAs)
X10293
V &
SDF 2.1
VHD &
SDF 2.1
Simulation
Libraries
CORE Generator
Schematic Capture
Constraints Editor
NGD
UCF
HDL
Symbol
NetGen
NGM & PCF
EDIF
2 0 0
MAP
Floorplanner
NGC
TRACE &
Timing Analyzer
PAR
BitGen
Synthesis Simulation
EDIF 2 0 0 &
Constraints/NCF
NGC
(XST Netlist)
NetGen
Testbench
Stimulus
NCD & PCF
NCD
NGDBuild NGDBuildNGDBuild
Synthesis
Libraries
Schematic
Libraries
BIT
iMPACT
PROMGen