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Development System Reference Guide www.xilinx.com 51
FPGA Design Tips
R
This circuit guarantees a minimum clock pulse width and it does not add skew to the clock.
The Spartan-II, and Virtex families’ flip-flops have a built-in clock-enable (CE).
Counters
Cascading several small counters to create a larger counter is similar to a gated clock. For
example, if two 8-bit counters are connected, the terminal counter (TC) of the first counter
is a large AND function gating the second clock input.
Figure 2-13: Synchronous Design Using Data Feedback
X9202
Enable
Clock
DQ
Clock
Enable
Output
a) Using a Feedback Path
b) Corresponding Timing Diagram
D