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Development System Reference Guide www.xilinx.com 269
BitGen Options
R
M1Pin
Adds an internal pull-up, pull-down or neither to the M1 pin. The following settings are
available. The default is PullUp.
Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M1 pin.
M2Pin
Adds an internal pull-up, pull-down or neither to the M2 pin. The default is PullUp. Select
Pullnone to disable both the pull-up resistor and pull-down resistor on the M2 pin.
Match_cycle
Specifies a stall in the Startup cycle until digitally controlled impedance (DCI) match
signals are asserted.
Note:
When the Auto setting is specified, BitGen searches the design for any DCI I/O standards. If
DCI standards exist, BitGen will use the Match_cycle:2 setting, otherwise it will use the
Match_cycle:NoWait setting.
PartialGCLK
Adds the center global clock column frames into the list of frames to write out in a partial
bitstream. This option is equivalent to the PartialMask0:1 option.
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullup, Pulldown, Pullnone
Default: Pullup
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullup, Pulldown, Pullnone
Default: Pullup
Architectures: Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3,
Spartan-3E
Settings: Auto, NoWait, 0, 1, 2, 3, 4, 5, 6
Default: NoWait
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Default: <Not Specified> - no partial masks in use