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Development System Reference Guide www.xilinx.com 419
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timing simulation
This type of simulation takes place after the HDL design has been
synthesized and placed and routed. The purpose of this simulation is
to check the dynamic timing behavior of the HDL design in the target
technology.
Use the block and routing delay information from the routed design
to assess the circuit behavior under worst-case conditions.
timing specifications
Timing specifications define the maximum allowable delay on any
given set of paths in a design. Timing specifications are entered on the
schematic.
TRACE
Provides static timing analysis of a design based on input timing
constraints.
trace information
Trace information is a list of nodes and vectors to be simulated in
functional and timing simulation. This information is defined at the
schematic level.
transistor
A transistor is a three-terminal semiconductor device that switches or
amplifies electrical current. It acts like a switch: On is equal to 1, and
Off is equal to 0.
trimming
Trimming is the process of removing unconnected or unused logic.
tristate (3-state)
A 3-state, or 3-state buffer, is a buffer that places an output signal in a
high-impedance state to prevent it from contending with another
output signal.
tristate (3-state) condition
A 3-state condition is a high-impedance state. A 3-state can act also as
a normal output; i.e. it can be on, off, or not connected.
truth table
A truth table defines the behavior for a block of digital logic. Each line
of a truth table lists the input signal values and the resulting output
value.
TSIM
A program that formats implemented CPLD design (VM6) files into a
format usable by the NetGen timing simulation flow.