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Development System Reference Guide www.xilinx.com 155
R
Chapter 8
Physical Design Rule Check
This program is compatible with the following families:
• Virtex
™
, Virtex
™
-E
• Virtex
™
-II
• Virtex
™
-II Pro, Virtex
™
-II Pro X
• Virtex
™
-4
• Virtex
™
-5 LX
• Spartan
™
-II, Spartan
™
-IIE
• Spartan
™
-3, Spartan
™
-3E, Spartan
™
-3L
The chapter describes the physical Design Rule Check program. This chapter contains the
following sections:
• “DRC Overview”
• “DRC Syntax”
• “DRC Input File”
• “DRC Output File”
• “DRC Options”
• “DRC Checks”
• “DRC Errors and Warnings”
DRC Overview
The physical Design Rule Check, also known as DRC, comprises a series of tests to
discover physical errors and some logic errors in the design. The physical DRC is run as
follows:
• MAP automatically runs physical DRC after it has mapped the design.
• PAR (Place and Route) automatically runs physical DRC on nets when it routes the
design.
• BitGen, which creates a a BIT file for programming the device, automatically runs
physical DRC.
• You can run physical DRC from within the FPGA Editor tool. The DRC also runs
automatically after certain FPGA Editor operations (for example, when you edit a
logic cell or when you manually route a net). For a description of how the DRC works
within the FPGA Editor, see the online help provided with the FPGA Editor GUI tool.
• You can run physical DRC from the UNIX or DOS command line.