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4 www.xilinx.com Development System Reference Guide
Preface: About This Guide
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• Chapter 7, “MAP”—MAP packs the logic defined by an NGD file into FPGA elements
such as CLBs, IOBs, and TBUFs.
• Chapter 8, “Physical Design Rule Check”—The physical Design Rule Check (DRC)
comprises a series of tests run to discover physical errors in your design.
• Chapter 9, “PAR”—PAR places and routes FPGA designs.
• Chapter 10, “XPower”—XPower is a power and thermal analysis tool that generates
power and thermal estimates after the PAR or CPLDfit stage of the design.
• Chapter 11, “PIN2UCF,”—PIN2UCF generates pin-locking constraints in a UCF file
by reading a a placed NCD file for FPGAs or GYD file for CPLDs.
• Chapter 12, “TRACE”—Timing Reporter and Circuit Evaluator (TRACE) performs
static timing analysis of a physical design based on input timing constraints.
• Chapter 13, “Speedprint”— Speedprint lists block delays for a specified device and its
speed grades.
• Chapter 14, “BitGen”—BitGen creates a configuration bitstream for an FPGA design.
• Chapter 15, “BSDLAnno”—BSDLAnno automatically modifies a BSDL file for post-
configuration interconnect testing.
• Chapter 16, “PROMGen” —PROMGen converts a configuration bitstream (BIT) file
into a file that can be downloaded to a PROM. PROMGen also combines multiple BIT
files for use in a daisy chain of FPGA devices.
• Chapter 17, “IBISWriter”—IBISWriter creates a list of pins used by the design, the
signals inside the device that connect those pins, and the IBIS buffer model that
applies to the IOB connected to the pins.
• Chapter 18, “CPLDfit” —CPLDfit reads in an NGD file and fits the design into the
selected CPLD architecture.
• Chapter 19, “TSIM” — TSIM formats an implemented CPLD design (VM6) into a
format usable by the NetGen timing simulation flow, which produces a back-
annotated timing file for simulation.
• Chapter 20, “TAEngine” —TAEngine performs static timing analysis on a successfully
implemented Xilinx CPLD design (VM6).
• Chapter 21, “Hprep6” —Hprep6 takes an implemented CPLD design (VM6) from
CPLDfit and generates a JEDEC (JED) programming file.
• Chapter 22, “NetGen”—NetGen reads in applicable Xilinx implementation files,
extracts design data, and generates netlists that are used with supported third-party
simulation, equivalence checking, and static timing analysis tools.
• Chapter 23, “XFLOW”—XFLOW automates the running of Xilinx implementation
and simulation flows.
• Chapter 24, “Data2MEM”—Data2MEM transforms CPU execution code, or pure data,
into Block RAM initialization records.
• “Appendix A”—This appendix gives an alphabetic listing of the files used by the
Xilinx Development System.
• “Appendix B” —This appendix describes the netlist reader, EDIF2NGD, and how it
interacts with NGDBuild.