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350 www.xilinx.com Development System Reference Guide
Chapter 23: XFLOW
R
Xilinx provides the following option files, which are targeted to specific vendors, for use
with this flow type.
The following example shows how to generate a Verilog functional simulation netlist for
an FPGA design.
xflow -p xc2v250fg256-5 -fsim generic_verilog.opt
testclk.v
–implement (Implement an FPGA)
–implement option_file
This flow type implements your design. It invokes the fpga.flw flow file and runs
NGDBuild, MAP, PAR, and then TRACE. It outputs a placed and routed NCD file.
Xilinx provides the following option files for use with this flow type. These files allow you
to optimize your design based on different parameters.
Table 23-7: Option Files for –fsim Flow Type
Option File Description
generic_vhdl.opt Generic VHDL
modelsim_vhdl.opt Modelsim VHDL
generic_verilog.opt Generic Verilog
modelsim_verilog.opt Modelsim Verilog
nc_verilog.opt NC Verilog
verilog_xl.opt Verilog-XL
vcs_verilog.opt VCS Verilog
nc_vhdl.opt NC VHDL
scirocco_vhdl.opt Scirocco VHDL
Table 23-8: Option Files for –implement Flow Type
Option Files Description
fast_runtime.opt Optimized for fastest runtimes at the
expense of design performance
Recommended for medium to slow
speed designs
balanced.opt Optimized for a balance between
speed and high effort
high_effort.opt Optimized for high effort at the
expense of longer runtimes
Recommended for creating designs
that operate at high speeds
overnight.opt Multi-pass place and route (MPPR)
overnight mode