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262 www.xilinx.com Development System Reference Guide
Chapter 14: BitGen
R
ActivateGCLK
Allows any partial bitstream for a reconfigurable area to have its registered elements wired
to the correct clock domain. Clock domains must be minimally defined in the NCD.
ActiveReconfig
Prevents the assertions of GHIGH and GSR during configuration. This is required for the
active partial reconfiguration enhancement features
.
Binary
Creates a binary file with programming data only. Use this option to extract and view
programming data. Any changes to the header will not affect the extraction process.
CclkPin
Adds an internal pull-up to the Cclk pin. The Pullnone setting disables the pullup.
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: No, Yes
Default: No
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: No, Yes
Default: No
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-
II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: No, Yes
Default: No
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-
II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullnone, Pullup
Default: Pullup