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Development System Reference Guide www.xilinx.com 325
NetGen Timing Simulation Flow
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–ofmt (Output Format)
-ofmt verilog|vhdl
The –ofmt option is a required option that specifies output format of either Verilog or
VHDL netlists.
–pcf (PCF File)
-pcf pcf_file.pcf
The –pcf option allows you to specify a PCF (physical constraints file) as input to NetGen.
You only need to specify a physical constraints file if prorating constraints (temperature
and/or voltage) are used.
Temperature and voltage constraints and prorated delays are described in the Constraints
Guide.
Note:
The –pcf option is valid for the timing simulation flow.
–s (Change Speed)
-s [speed grade]
The –s option instructs NetGen to annotate the device speed grade you specify to the
netlist. The device speed can be entered with or without the leading dash. For example, both
–s 3 and –s –3 are allowable entries.
Some architectures support the –s min option. This option instructs NetGen to annotate a
process minimum delay, rather than a maximum worst-case to the netlist. The command
line syntax is the following.
-s min
Minimum delay values may not be available for all families. Use the Speedprint or
PARTGen utility programs in the software to determine whether process minimum delays
are available for your target architecture. See Chapter 4, “PARTGen” and Chapter 13,
“Speedprint” for additional information.
Settings made with the –s min option override any prorated timing parameters in the PCF.
If –s min is used then all fields (MIN:TYP:MAX) in the resulting SDF file are set to the
process minimum value.
Note:
The –s option is valid for the timing simulation flow.
–sim (Generate Simulation Netlist)
The -sim option writes a simulation netlist. This is the default option for NetGen, and the
default option for NetGen for generating a simulation netlist.
–tb (Generate Testbench Template File)
The –tb option generates a testbench file with a .tb extension. It is a ready-to-use Verilog or
VHDL template file, based on the input NCD file. The type of template file (Verilog or
VHDL) is specified with the –ofmt option.