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222 www.xilinx.com Development System Reference Guide
Chapter 12: TRACE
R
In the following figure, the clock skew Tsk is the delay from the clock input (CLKIOB) to
register D (TclkD) less the delay from the clock input (CLKIOB) to register S (TclkS).
Negative skew relative to the destination reduces the amount of time available for the data
path, while positive skew relative to the destination register increases the amount of time
available for the data path.
Table 12-2: Clock Skew and Setup Checking Terminology
Terms Definition
constraint The required time interval for the path, either specified explicitly by you
with a FROM TO constraint, or derived from a PERIOD constraint.
Tpath The summation of component and connection delays along the path.
Tsu (setup) The setup requirement for the destination register.
Tsk (skew) The difference between the arrival time for the destination register and
the source register.
Slack The negative slack shows that a setup error may occur, because the data
from the source register does not set up at the target register for a
subsequent clock edge.
Figure 12-2: Clock Skew Example
Interconnect
and Logic
S D
CLKIOB
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