Xilinx 8.2i Life Jacket User Manual


 
150 www.xilinx.com Development System Reference Guide
Chapter 7: MAP
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Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:LIT - Logical network Inst_dcm1_CLKIN_IBUFG_OUT has no load.
WARNING:LIT - The above warning message base_net_load_rule is repeated
1 more time for the following:
N0
To see the details of these warning messages, please use the -detail
switch.
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using
slew rate limited output drivers. The delay on speed critical single
ended outputs can be dramatically reduced by designating them as fast
outputs in the schematic.
Section 4 - Removed Logic Summary
---------------------------------
1 block(s) removed
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Unused block "xcounter/VCC" (ONE) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
GND xcounter/GND
To enable printing of redundant blocks removed and signals merged, set
the
detailed map report option and rerun map.