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Development System Reference Guide www.xilinx.com 301
CPLDfit Options
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CPLDfit Options
CPLDfit uses the following option files:
–blkfanin (Specify Maximum Fanin for Function Blocks)
-blkfanin [limit:4,40]
The -blkfanin option specifies the maximum number of function block inputs to use when
fitting a device. If the value is near the maximum, this option reduces the possibility that
design revisions will be able to fit without changing the pin-out. The maximum values
vary with each supported CPLD architecture as shown below (default in parentheses):
CoolRunner XPLA3 = 40 (38)
CoolRunner-II = 40 (36)
–exhaust (Enable Exhaustive Fitting)
The values for inputs and pterms have an impact on design fitting. Occasionally different
values must be tried before a design is optimally fit. The -exhaust option automates this
process by iterating through all combinations of input and pterm limits until a fit is found.
This process can take several hours depending on the size of the design. This option is off
by default.
–ignoredatagate (Ignore DATA_GATE Attributes)
This option directs CPLDfit to ignore the DATA_GATE attribute when fitting a
CoolRunner-II device. This option is off by default.
Architecture Support: CoolRunner-II
–ignoretspec (Ignore Timing Specifications)
CPLDfit optimizes paths to meet timing constraints. The -ignoretspec option directs
CPLDfit to not perform this prioritized optimization. This option is off by default.
–init (Set Power Up Value)
-init [low|high|fpga]
The -init option specifies the default power up state of all registers. This option is
overridden if an INIT attribute is explicitly placed on a register. Low and high are self-
explanatory. The FPGA setting causes all registers with an asynchronous reset to power up
low, all registers with an asynchronous preset to power up high, and remaining registers
to power up low. The default setting is low.