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Development System Reference Guide www.xilinx.com 317
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Chapter 22
NetGen
The NetGen program is compatible with the following families:
• Virtex
™
, Virtex
™
-E
• Virtex
™
-II
• Virtex
™
-II Pro, Virtex
™
-II Pro X
• Virtex
™
-4
• Virtex
™
-5 LX
• Spartan
™
-II, Spartan
™
-IIE
• Spartan
™
-3, Spartan
™
-3E, Spartan
™
-3L
• CoolRunner
™
XPLA3, CoolRunner
™
-II
• XC9500
™
, XC9500XL
™
, XC9500XV
™
This chapter describes the NetGen program and contains the following sections:
• “NetGen Overview”
• “NetGen Simulation Flow”
• “NetGen Functional Simulation Flow”
• “NetGen Timing Simulation Flow”
• “NetGen Equivalence Checking Flow”
• “NetGen Static Timing Analysis Flow”
• “Preserving and Writing Hierarchy Files”
• “Dedicated Global Signals in Back-Annotation Simulation”
NetGen Overview
The NetGen application is a command line executable that reads Xilinx design files as
input, extracts data from the design files, and generates netlists that are used with
supported third-party simulation, equivalence checking, and static timing analysis tools.
NetGen supports the following flow types:
• Functional Simulation for FPGA and CPLD designs
• Timing Simulation for FPGA and CPLD designs
• Equivalence Checking for FPGA designs
• Static Timing Analysis for FPGA designs