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324 www.xilinx.com Development System Reference Guide
Chapter 22: NetGen
R
Note: Do not use GR, GSR, PRLD, PRELOAD, or RESET as port names, because these are
reserved names in the Xilinx software. This option is ignored by UNISIM-based flows, which use an
NGC file as input.
–insert_pp_buffers (Insert Path Pulse Buffers)
–insert_pp_buffers true|false
The –insert_pp_buffers option controls whether path pulse buffers are inserted into the
output netlist to eliminate pulse swallowing. Pulse swallowing is seen on signals in back-
annotated timing simulations when the pulse width is shorter than the delay on the input
port of the component. For example, if a clock of period 5 ns (2.5 ns high/2.5 ns low) is
propagated through a buffer, but in the SDF, the PORT or IOPATH delay for the input port
of that buffer is greater than 2.5 ns, the output will be unchanged in the waveform window
(e.g., if the output was "X" at the start of simulation, it will remain at "X").
By default this command is set to false.
Note:
This option is available when the input is an NCD file.
–intstyle (Integration Style)
–intstyle {ise | xflow | silent}
The –intstyle option reduces screen output based on the integration style you are running.
When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent.
The mode sets the way information is displayed in the following ways:
–intstyle ise
This mode indicates the program is being run as part of an integrated design
environment.
–intstyle xflow
This mode indicates the program is being run as part of an integrated batch flow.
–intstyle silent
This mode limits screen output to warning and error messages only.
Note:
The -intstyle option is automatically invoked when running in an integrated environment, such
as Project Navigator or XFLOW.
–mhf (Multiple Hierarchical Files)
The –mhf option is used to write multiple hierarchical files--one for every module that has
the KEEP_HIERARCHY attribute.
Note:
See “Preserving and Writing Hierarchy Files” for additional information.
–module (Simulation of Active Module)
–module
The –module option creates a netlist file based on the active module only, independent of
the top-level design. NetGen constructs the netlist based only on the active module’s
interface signals.
To use this option you must specify an NCD file that contains an expanded active module.
Note:
The –module option is for use with the Modular Design flow.