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Development System Reference Guide www.xilinx.com 149
MAP Report (MRP) File
R
• Configuration String Information—This section, produced with the -detail option,
shows configuration strings and programming properties for special components like
DCMs, BRAMS, GTs and similar components. Configuration strings for slices and
IOBs marked “SECURE” are not shown.
• Additional Device Resource Counts—This section contains raw design statistics for
Xilinx analysis purposes.
Note:
The MAP Report is formatted for viewing in a monospace (non-proportional) font. If the text
editor you use for viewing the report uses a proportional font, the columns in the report do not line up
correctly.
Release 8.1i Map
Xilinx Mapping Report File for Design 'stopwatch'
Design Information
------------------
Command Line : C:/xilinx/bin/nt/map.exe -ise
c:\xilinx\projects\watchver\watchver.ise
-intstyle ise -p xc2v40-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o
stopwatch_map.ncd stopwatch.ngd stopwatch.pcf
Target Device : xc2v40
Target Package : fg256
Target Speed : -5
Mapper Version : virtex2 -- $Revision: 1.26.6.3 $
Mapped Date : Mon Nov 01 18:11:26 2005
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Logic Utilization:
Number of Slice Flip Flops: 17 out of 512 3%
Number of 4 input LUTs: 54 out of 512 10%
Logic Distribution:
Number of occupied Slices: 29 out of 256 11%
Number of Slices containing only related logic: 29 out of 29 100%
Number of Slices containing unrelated logic: 0 out of 29 0%
Total Number 4 input LUTs: 54 out of 512 10%
Number of bonded IOBs: 27 out of 88 30%
Number of GCLKs: 1 out of 16 6%
Number of DCMs: 1 out of 4 25%
Number of RPM macros: 1
Total equivalent gate count for design: 7,487
Additional JTAG gate count for IOBs: 1,296
Peak Memory Usage: 98 MB