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Development System Reference Guide www.xilinx.com 333
NetGen Static Timing Analysis Flow
R
The –ne option replaces invalid characters with underscores, so that name escaping does
not occur. For example, the net name “p1$40/empty” becomes “p1$40_empty” when
name escaping is not used. The leading backslash does not appear as part of the identifier.
The resulting Verilog file can be used if a vendor’s Verilog software cannot interpret
escaped identifiers correctly.
–ngm (Design Correlation File)
–ngm [ngm_file]
The -ngm option is used to specify an NGM design correlation file. This option is used for
equivalence checking flows.
–tm (Top Module Name)
–tm top_module_name
By default (without the –tm option), the output files inherit the top module name from the
input NCD or NGM file. The –tm option changes the name of the top-level module name
appearing within the NetGen output files.
–w (Overwrite Existing Files)
The –w option causes NetGen to overwrite the .v file if it exists. By default, NetGen does
not overwrite the netlist file.
Note:
All other output files are automatically overwritten.
NetGen Static Timing Analysis Flow
This section describes the NetGen Static Timing Analysis flow, which is used for analyzing
the timing, including minimum of maximum delay values, of FPGA designs.
Minimum of maximum delays are used by static timing analysis tools to calculate skew,
setup and hold values. Minimum of maximum delays are the minimum delay values of a
device under a specified operating condition (speed grade, temperature and voltage). If
the operating temperature and voltage are not specified, then the worst case temperature
and voltage values are used. Note that the minimum of maximum delay value is different
from the process minimum generated by using the –s min option.
The following example shows DELAY properties containing relative minimum and
maximum delays.
Note:
Both the TYP and MAX fields contain the maximum delay.
(DELAY)
(ABSOLUTE)
(PORT I (234:292:292) (234:292:292))
(IOPATH I O (392:489:489) (392:489:489))
Note: Timing simulation does not contain any relative delay information, instead the MIN, TYP, and
MAX fields are all equal.
NetGen uses the Static Timing Analysis flow to generate Verilog and SDF netlists
compatible with supported static timing analysis tools.