Xilinx 8.2i Life Jacket User Manual


 
264 www.xilinx.com Development System Reference Guide
Chapter 14: BitGen
R
DCIUpdateMode
This option controls how often the Digitally Controlled Impedance circuit attempts to
update the impedance match for DCI IOSTANDARDs. This option is preferable to the
FreezeDCI option because it has no effect on bitstream size and can be used with
Encrypted bitstreams. The setting DCIUpdateMode:Quiet supersedes the setting
FreezeDCI:Yes.
DCMShutdown
When DCMShutdown is enabled, the digital clock manager (DCM) resets if the
SHUTDOWN and AGHIGH commands are loaded into the configuration logic.
DebugBitstream
If the device does not configure correctly, you can debug the bitstream using the
DebugBitstream option. A debug bitstream is significantly larger than a standard
bitstream. The values allowed for the DebugBitstream option are No and Yes.
Note:
Use this option only if your device is configured to use slave or master serial mode.
In addition to a standard bitstream, a debug bitstream offers the following features:
Writes 32 0s to the LOUT register after the synchronization word
Loads each frame individually
Performs a cyclical redundancy check (CRC) after each frame
Writes the frame address to the LOUT register after each frame
Architectures: Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3E
Settings: As required, continuous, quiet
Default: As required
Architectures: Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3,
Spartan-3E
Settings: Disable, Enable
Default: Disable
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro,
Spartan-II, Spartan-IIE, Virtex-4, Spartan-3,
Spartan-3E
Values: No, Yes