Filter
Top Products
Development System Reference Guide www.xilinx.com 403
R
E
EDA
Electronic Design Automation (EDA). A generic name for all methods
of entering and processing digital and analog designs for further
processing, simulation, and implementation.
edge decoder
An edge decoder is a decoder whose placement is constrained to
precise positions within a side of the FPGA device.
EDIF
EDIF is the Electronic Data Interchange Format, an industry standard
file format for specifying a design netlist. It is generated by a third-
party design-entry tool. In the Xilinx M1 flow, EDIF is the standard
input format.
effort level
Effort level refers to how hard the Xilinx Design System (XDS) tries to
place a design. The effort level settings are.
High, which provides the highest quality placement but requires the
longest execution time. Use high effort on designs that do not route or
do not meet your performance requirements.
Medium, which is the default effort level. It provides the best trade-off
between execution time and high quality placement for most designs.
Low, which provides the fastest execution time and adequate
placement results for prototyping of simple, easy-to-route designs.
Low effort is useful if you are exploring a large design space and only
need estimates of final performance.
ENRead
Mentor Graphics EDIF netlist reader. Translates an EDIF netlist into
an EDDM single object.
entity
An entity is a set of interconnected components.