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Development System Reference Guide www.xilinx.com 409
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instance
An instance is one specific gate or hierarchical element in a design or
netlist. The term "symbol" often describes instances in a schematic
drawing. Instances are interconnected by pins and nets. Pins are ports
through which connections are made from an instance to a net. A
design that is flattened to its lowest level constituents is described
with primitive instances.
instantiation
Instantiation is the act of placing a symbol that represents a primitive
or a macro in a design or netlist.
Integrated Synthesis Environment (ISE)
ISE is an integrated tool suite that enables you to produce, test, and
implement designs for Xilinx FPGAs or CPLDs.
interconnect
Interconnect is the metal in a device that is used to implement the nets
of the design.
interconnect line
An interconnect line is any portion of a net.
IOB (input/output block)
An IOB is a collection or grouping of basic elements that implement
the input and output functions of an FPGA device.
I/O pads
I/O pads are the input/output pads that interface the design logic
with the pins of the device.
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JEDEC
JEDEC is a CPLD file format used for downloading device bitmap
information to a device programmer.
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latch
A latch is a two-state buffer fed by two inputs, D and L. When the L
input is Low, it acts as a transparent input; in this case, the latch acts
as a buffer and outputs the value input by D. When the L input is
High, it ignores the D input value.