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Development System Reference Guide www.xilinx.com 323
NetGen Timing Simulation Flow
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• V file—This is a IEEE 1364-2001 compliant Verilog HDL file that contains netlist
information obtained from the input NGA file. This file is a simulation model of the
fitted design and cannot be synthesized or used in any manner other than simulation.
• VHD file—This VHDL IEEE 1076.4 VITAL-2000 compliant VHDL file contains netlist
information obtained from the input NGA file. This file is a simulation model of the
fitted design and cannot be synthesized or used in any other manner than simulation.
Options for NetGen Simulation Flow
This section describes the supported NetGen command line options for timing simulation.
–aka (Write Also-Known-As Names as Comments)
–aka
The –aka option includes original user-defined identifiers as comments in the VHDL
netlist. This option is useful if user-defined identifiers are changed because of name
legalization processes in NetGen.
–bd (Block RAM Data File)
–bd [filename] [.elf|.mem] [tag [tagname]}
The –bd option specifies the path and file name of the .elf file used to populate the Block
RAM instances specified in the .bmm file. The address and data information contained in
the .elf (from EDK) or .mem file allows Data2MEM to determine which ADDRESS_BLOCK
to place the data. Multiple use of the -bd option is allowed.
Optionally, a tagname can be specified with the –bd option. If a tagname is specified, only
the address spaces with the same name in the .bmm file are used for translation, and all
other data outside of the tagname address spaces are ignored. See Chapter 24,
“Data2MEM” for additional information.
–dir (Directory Name)
–dir [directory_name]
The –dir option specifies the directory in which the output files are written.
–fn (Control Flattening a Netlist)
–fn
The –fn option outputs a flattened netlist. A flat netlist is without any design hierarchy.
–gp (Bring Out Global Reset Net as Port)
–gp port_name
The –gp option causes NetGen to bring out the global reset signal (which is connected to all
flip-flops and latches in the physical design) as a port on the top-level design module.
Specifying the port name allows you to match the port name you used in the frontend.
This option is used only if the global reset net is not driven. For example, if you include a
STARTUP_VIRTEX component in a Virtex-E design, you should not enter the –gp option,
because the STARTUP_VIRTEX component drives the global reset net.