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Project Properties and Options
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Table 3-9: MAP Options
Option Name Implementation Tool
“Allow Logic Optimization Across Hierarchy” MAP
“CLB Pack Factor Percentage” MAP
“Disable Register Ordering” MAP
“Equivalent Register Removal” MAP
“Extra Effort” MAP
“Generate Detailed MAP Report” MAP
“Global Optimization” MAP
“Map Effort Level” MAP
“Map Guide Design File (.ncd)” MAP
“Map Guide Mode” MAP
“Map Slice Logic into Unused Block RAMs” MAP
“Map to Input Functions” MAP
“Optimization Strategy (Cover Mode)” MAP
“Other Map Command Line Options” MAP
“Pack I/O Registers/Latches into IOBs” MAP
“Perform Timing-Driven Packing and Placement” MAP
“Register Duplication” MAP
“Replicate Logic to Allow Logic Level Reduction” MAP
“Retiming” MAP
“Starting Placer Cost Table (1-100)” MAP
“Trim Unconnected Signals” MAP
“Use RLOC Constraints” MAP