Xilinx 8.2i Life Jacket User Manual


 
Development System Reference Guide www.xilinx.com 263
BitGen Options
R
Compress
This option uses the multiple frame write feature in the bitstream to reduce the size of the
bitstream, not just the .bit file. Using the Compress option does not guarantee that the size
of the bitstream will shrink. Compression is enabled by setting the BitGen option –g
compress; compression is disabled by not setting it.
Note that the partial bit files generated with the BitGen –r setting automatically make use
of the multiple frame write feature, and are compressed bitstreams.
ConfigRate
Virtex/-E/-II/-II Pro and Spartan-II/-IIE/-3 use an internal oscillator to generate the
configuration clock, CCLK, when configuring in a master mode. Use the configuration rate
option to select the rate for this clock.
Note:
For a list of specific architecture settings, use the bitgen -h [architecture]
command.The default value may vary by architecture.
CRC
The CRC option controls the generation of a Cyclic Redundancy Check value in the
bitstream. When enabled, a unique CRC value is calculated based on bitstream contents. If
the calculated CRC value does not match the CRC value in the bitstream, the device will
fail to configure. When CRC is disabled a constant value is inserted in the bitstream in
place of the CRC and the device will not calculate a CRC.
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-
II, Spartan-IIE, Virtex-4, Spartan-3
Settings: None
Default: Off
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan 3, Spartan-3E
Settings 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60
Default: 4
Settings for
Spartan-3/-3E
6, 3, 12, 25, 50, 100 (default is 6)
Default for
Spartan-3:
6
Architectures: Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3,
Spartan-3E
Settings: Disable, Enable
Default: Enable