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136 www.xilinx.com Development System Reference Guide
Chapter 7: MAP
R
Note: The Incremental Design flow is being deprecated and will not be available in future releases
of Xilinx software. New in 8.2i are Partitions, which provide significant flexibility and functionality for
design preservation. Information on Partitions can be found in the online help included in the 8.2i
software and in the “TCL chapter” of this book. Incremental Design using the map and par -gm
incremental option will still work in 8.2i, though it generates a warning that this flow is being removed.
–ignore_keep_hierarchy (Ignore KEEP_HIERARCHY Properties)
Map also supports the –ignore_keep_hierarchy option that ignores any
"KEEP_HIERARCHY" properties on blocks.
–intstyle (Integration Style)
–intstyle {ise | xflow | silent}
The –intstyle option reduces screen output based on the integration style you are running.
When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent.
The mode sets the way information is displayed in the following ways:
–intstyle ise
This mode indicates the program is being run as part of an integrated design
environment.
–intstyle xflow
This mode indicates the program is being run as part of an integrated batch flow.
–intstyle silent
This mode limits screen output to warning and error messages only.
Note:
The -intstyle option is automatically invoked when running in an integrated environment, such
as Project Navigator or XFLOW.
–ir (Do Not Use RLOCs to Generate RPMs)
If you enter the –ir option, MAP uses RLOC constraints to group logic within CLBs, but
does not use the constraints to generate RPMs (Relationally Placed Macros) controlling the
relative placement of CLBs. Stated another way, the RLOCs are not used to control the
relative placement of the CLBs with respect to each other.
For the Spartan architectures, the –ir option has an additional behavior; the RLOC
constraint that cannot be met is ignored and the mapper will continue processing the
design. A warning is generated for each RLOC that is ignored. The resulting mapped
design is a valid design.
–ise (ISE Project File)
–ise project_file
The –ise option specifies an ISE project file, which can contain settings to capture and filter
messages produced by the program during execution.
–k (Map to Input Functions)
The syntax for Spartan-II, Spartan-IIE, Virtex, and Virtex-E architectures follows:
–k
{4 |5 |6}