Filter
Top Products
70 www.xilinx.com Development System Reference Guide
Chapter 3: Tcl
R
speed_grade specifies the speed for the target device of the current ISE project.
set top (set the top-level module/entity)
The project set top command specifies the top-level module or entity in the design hierarchy.
To use this command, you must first add the module or entity to your project with the xfile
add command.
% project set top <module_name>
project is the name of the Xilinx Tcl command.
set top is the name of the project subcommand.
module_name specifies the name for the top-level module for Verilog and EDIF-based
designs.
For VHDL designs, you must specify the architecture name and the entity name using the
following syntax:
% project set top <architecture_name> [entity_name]
timing_analysis (generate timing analysis reports)
The timing_analysis command generates static timing analysis reports for an implemented
design.
% timing_analysis <subcommand> <analysis_name>
delete (delete timing analysis)
The timing_analysis delete command removes a previously created analysis from the current
ISE project.
% timing_analysis delete <analysis_name>
timing_analysis is the name of the Xilinx Tcl command.
delete is the name of the timing_analysis subcommand.
Example: % project set speed -7
Description: In this example, the device speed for the current project is set to -7.
Tcl Return: The previous value. In this example, the previous speed grade
setting is returned.
Example: % project set top pong_top
Description: In this Verilog example, the project set top command is used to set
pong_top as the top-level module in the design hierarchy.
Tcl Return: The name of the previous top-level module.