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Development System Reference Guide www.xilinx.com 129
R
Chapter 7
MAP
This program is compatible with the following families:
• Virtex
™
, Virtex
™
-E
• Virtex
™
-II
• Virtex
™
-II Pro, Virtex
™
-II Pro X
• Virtex
™
-4
• Virtex
™
-5 LX
• Spartan
™
-II, Spartan
™
-IIE
• Spartan
™
-3, Spartan
™
-3E, Spartan
™
-3L
This chapter describes the MAP program, which is used during the implementation
process to map a logical design to a Xilinx FPGA. This chapter contains the following
sections:
• “MAP Overview”
• “MAP Syntax”
• “MAP Input Files”
• “MAP Output Files”
• “MAP Options”
• “MAP Process”
• “Register Ordering”
• “Guided Mapping”
• “Simulating Map Results”
• “MAP Report (MRP) File”
• “Halting MAP”
MAP Overview
The MAP program maps a logical design to a Xilinx FPGA. The input to MAP is an NGD
file, which is generated using the NGDBuild program. The NGD file contains a logical
description of the design that includes both the hierarchical components used to develop
the design and the lower level Xilinx primitives. The NGD file also contains any number of
NMC (macro library) files, each of which contains the definition of a physical macro.
MAP first performs a logical DRC (Design Rule Check) on the design in the NGD file. MAP
then maps the design logic to the components (logic cells, I/O cells, and other
components) in the target Xilinx FPGA.