Xilinx 8.2i Life Jacket User Manual


 
Development System Reference Guide www.xilinx.com 247
PERIOD Constraints
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PERIOD Constraints
A PERIOD constraint identifies all paths between all sequential elements controlled by the
given clock signal name. For additional information on timing constraints, please refer to
the Constraints Guide.
PERIOD Constraints Examples
The following section provides examples and details of the PERIOD constraints shown in
the Timing Constraints section of a timing analysis report. For clarification, PERIOD
constraint information is divided into the following parts:
PERIOD Header
PERIOD Path
PERIOD Path Details
PERIOD Constraint with PHASE
PERIOD Header
This following example is of a constraint generated using NGDbuild during the translate
step in the Xilinx design flow. A new timespec (constraint) name was created. In this
example it is TS_write_dcm_CLK0. Write_dcm is the instantiated name of the DCM. CLK0
is the output clock. The timegroup created for the PERIOD constraint is write_dcm_CLK0.
The constraint is related to TS_wclk. In this example, the PERIOD constraint is the same as
the original constraint because the original constraint is multiplied by 1 and there is not a
phase offset. Because TS_wclk is defined to have a Period of 12 ns, this constraint has a
Period of 12 ns.
In this constraint, 296 items are analyzed. An item is a path or a net. Because this
constraint deals with paths, an item refers to a unique path. If the design has unique paths
to the same endpoints, this is counted as two paths. If this constraint were a MAXDELAY
or a net-based constraint, items refer to nets. The number of timing errors refers to the
number of endpoints that do not meet the timing requirement, and the number of
endpoints with hold violations. If the number of hold violations is not shown, there are no
hold violations for this constraint. If there are two or more paths to the same endpoint, it is
considered one timing error. If this is the situation, the report shows two or more detailed
paths; one for each path to the same endpoint.
The next line reports the minimum Period for this constraint, which is how fast this clock
runs.
Example:
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Timing constraint: TS_write_dcm_CLK0 = PERIOD TIMEGRP "write_dcm_CLK0"
TS_wclk *
1.000000 HIGH
50.000 % ;
296 items analyzed, 0 timing errors detected.
Minimum period is 3.825ns.
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