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Development System Reference Guide www.xilinx.com 211
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Chapter 12
TRACE
The Timing Reporter and Circuit Evaluator (TRACE) program is compatible with the
following device families:
• Virtex
™
, Virtex
™
-E
• Virtex
™
-II
• Virtex
™
-II Pro/X
• Virtex
™
-4
• Virtex
™
-5 LX
• Spartan
™
, Spartan
™
-II, Spartan
™
-IIE
• Spartan
™
-3, Spartan
™
-3E, Spartan
™
-3L
• CoolRunner
™
XPLA3, CoolRunner
™
-II
• XC9500
™
, XC9500XL
™
, XC9500XV
™
This chapter contains the following sections:
• “TRACE Overview”
• “TRACE Syntax”
• “TRACE Input Files”
• “TRACE Output Files”
• “TRACE Options”
• “TRACE Command Line Examples”
• “TRACE Reports”
• “OFFSET Constraints”
• “PERIOD Constraints”
• “Halting TRACE”
TRACE Overview
TRACE provides static timing analysis of an FPGA design based on input timing
constraints.
TRACE performs two major functions.
• Timing Verification—Verifies that the design meets timing constraints.
• Reporting—Generates a report file that lists compliance of the design against the
input constraints. TRACE can be run on unplaced designs, only placed designs,
partially placed and routed designs, and completely placed and routed designs.