Filter
Top Products
Development System Reference Guide www.xilinx.com 373
R
Appendix A
Xilinx Development System Files
This appendix gives an alphabetic listing of the files used by the Xilinx development
system.
Name Type Produced By Description
BIT Data BitGen Download bitstream file for
devices containing all of the
configuration information from the
NCD file
BGN ASCII BitGen Report file containing information
about a BitGen run
BLD ASCII NGDBuild Report file containing information
about an NGDBuild run, including
the subprocesses run by NGDBuild
DATA C File TRCE File created with the –stamp option
to TRCE that contains timing
model information
DC ASCII Synopsys FPGA
Compiler
Synopsys setup file containing
constraints read into the Xilinx
Development System
DLY ASCII PAR File containing delay information
for each net in a design
DRC ASCII BitGen Design Rule Check file produced
by BitGen
EDIF (various
file extensions)
ASCII CAE vendor’s EDIF 2
0 0 netlist writer.
EDIF netlist. The Xilinx
Development System accepts an
EDIF 2 0 0 Level 0 netlist file
EDN ASCII NGD2EDIF Default extension for an EDIF
2 0 0 netlist file
ELF ASCII Used for NetGen This file populates the Block RAMs
specified in the .bmm file.